D flipflop with built in edge detection in circuit network

This implements the equivalent of a real life D flipflop.

The D input is the data, which can be either 0 (logic LOW) or 1 (logic HIGH)

The C input is for a clock signal, something like https://factorioprints.com/view/-OEpibzz0yCS_H6Z_-0K

Built in edge detection, so this will only latch the input on the rising edge of the clock

There are 2 outputs, Q (latched HIGH) and inverse Q (latched LOW)